1. Field of the Invention
The present invention relates to a digital matched filter and a mobile wireless terminal employing the digital matched filter. In particular, the invention relates to a digital matched filter to perform despreading at the receiving end in a direct sequence spread spectrum communication system as well as a mobile wireless terminal including such a digital matched filter.
2. Description of the Related Art
In digital radio communication like that of CDMA (Code Division Multiple Access) system, for example, direct sequence spread spectrum communication system has conventionally been employed. In the direct sequence spread spectrum communication system, digital transmission data is scrambled by a spreading code sequence specific to each user and then transmitted, and the receiving end descrambles the received digital data by a despreading code sequence.
At the transmitting end of the digital radio communication using such direct sequence spread spectrum communication system, a spreading unit is provided for generating a spreading code sequence to scramble digital transmission data. At the receiving end, a despreading unit is provided for generating a replica signal of the spreading code sequence to descramble received digital data.
This direct sequence spread spectrum communication system requires the timing of generating a spreading code at the receiving end to be synchronized with the timing of generating a spreading code at the transmitting end.
FIG. 14 is a schematic block diagram showing a basic structure of a transmitter and a receiver in the direct sequence spread spectrum communication system as discussed above.
Referring to FIG. 14, the direct sequence spread spectrum communication system is basically constituted of transmitter 60 and receiver 65.
In transmitter 60, an original signal to be transmitted is supplied to a primary modulator 61 to narrow the bandwidth of the signal in terms of effective use of radio waves.
An output of primary modulator 61 is supplied to a spreading unit 62 to be spread, i.e., scrambled (secondary modulation) by a spreading code sequence supplied from a spreading code generating unit (not shown) provided therein.
An output of spreading unit 62 is processed as required for radio communication by a transmission circuit (not shown) and then transmitted via an antenna 63.
The signal transmitted from antenna 63 is received by an antenna 64 of receiver 65 to be processed by a reception circuit (not shown) as required for radio reception and then supplied to a despreading unit 66.
Despreading unit 66 despreads, i.e., descrambles the received signal by a replica signal synchronized with the spreading code sequence at the transmitting end, that is supplied from a spreading code generating unit (not shown) provided therein.
The original signal is thus derived from despreading unit 66 and demodulated by a demodulating unit 67.
In order to achieve despreading at the receiver side in synchronism with the transmitter side, despreading unit 66 at the receiver side must shift the spreading code sequence of the receiver side to eliminate timing difference between the spreading code sequence at the receiver and that at the transmitter and accordingly establish initial synchronism with the spreading code sequence of the transmitter side.
FIG. 15 is a schematic block diagram showing a conventional initial synchronizing circuit for accomplishment of such initial synchronism and its control circuit.
Initial synchronizing circuit 70 and control circuit 80 shown in FIG. 15 are included in despreading unit 66 in FIG. 14. Initial synchronizing circuit 70 includes a digital matched filter 71, a cyclic integration unit 72 and a synchronism acquisition decision unit 73.
Digital matched filter 71 is employed because of its superior peak detection speed for a correlation value between a received signal and a spreading code. The digital matched filter is discussed in detail for example by Tachika in “Digital Matched Filter Technique in Spread Spectrum Communication and its Problems,”IEICE Technical Report SST 62-21.
Digital matched filter 71 calculates a correlation value between a received input signal and a replica signal of the spreading code sequence generated therein to output the resultant value as a despread signal. The despread signal thus output is supplied to demodulating unit 67 in FIG. 14 as well as cyclic integration unit 72. Details of the structure and operation of conventional digital matched filter 71 are discussed later.
It is noted that the spreading code sequence is formed of spreading codes repeated in a certain repetition period and this repetition period of the spreading codes is hereinafter referred to “frame.”
Cyclic integration unit 72 determines an integral of correlation values supplied from digital matched filter 71 over a period of several frames of a spreading code sequence to average the correlation values, in order to eliminate noise and improve accuracy of detecting the peak value of the correlation values.
Here, the energy of a received signal per one bit of information is represented by Eb and the density of noise and interference signals per 1 Hz is represented by No. If Eb/No indicates a large value, it means that the energy of the received signal is relatively high, so that the peak value of correlation values in each frame is easily detected. However, if Eb/No is small, it means a relatively low energy of the received signal and thus detection is difficult of the peak value of correlation values as they are in each frame.
Then, the accuracy of peak detection of correlation values can be improved by averaging correlation values of multiple frames even if Eb/No is small. A digital matched filter using this cyclic integration is discussed in detail, for example, by Tachika et al in “DS/GMSK/PSK System Using Four-Phase Correlator and Spread Spectrum Demodulation LSI,” IEICE Technical Report SST96-26.
Referring again to FIG. 15, the integral of the correlation values determined by cyclic integration unit 72 is supplied to synchronism acquisition decision unit 73. Synchronism acquisition decision unit 73 decides whether the supplied integral of the correlation values is greater than a threshold value set therein in advance.
Specifically, if the peak of correlation values resultant from the averaging exceeds the threshold value, a signal indicating this (e.g. “1”) is supplied to control unit 80. If there is no correlation value peak exceeding the threshold value, a signal indicating this (e.g. “0”) is supplied to control unit 80.
If a signal “1” is supplied from synchronism acquisition decision unit 73, control unit 80 finds that the phase difference between respective spreading code sequences of the transmitter and the receiver is within an error corresponding to “a fraction of operating frequency of digital matched filter 71” namely that rough synchronism is accomplished, and accordingly controls timing of generating a spreading code sequence by digital matched filter 71 such that the spreading code sequence generation timing for despreading is maintained.
If a signal “0” is supplied from synchronism acquisition decision unit 73, control unit 80 finds that the phase difference between respective spreading code sequences of the transmitter and the receiver is greater than the error corresponding to “a fraction of operating frequency of digital matched filter 71” namely that rough synchronism is not achieved, and then controls generation timing of a spreading code sequence by digital matched filter 71 such that the generation timing of a spreading code sequence for despreading is shifted to establish rough synchronism. The timing of generating spreading codes is controlled more specifically by rewriting a spreading code register value (tap coefficient) or updating a received signal storage register value.
Control unit 80 monitors output of synchronism acquisition decision circuit 73 even after the rough synchronism is established so as to control spreading code sequence generation timing by digital matched filter 71 and accordingly maintain the rough synchronism. In this way, the initial synchronism is achieved.
The structure and operation of digital matched filter 71 shown in FIG. 15 are now described in detail below.
FIG. 16 is a block diagram showing a structure of a transversal filter as one example of digital matched filter 71. Referring to FIG. 16, in the structure of a spreading code replica generator 71a, an initial value specific to the system is set in a shift register (not shown) having a structure based on a predetermined generating polynomial, shifting operation is performed a predetermined number of times based on the initial value, and then resultant codes are output successively as a spreading code sequence known to the transmitter and receiver sides.
Chips corresponding to one frame of spreading codes generated by spreading code replica generator 71a are input to a spreading code register for input 71b at a chip rate of the spreading codes and then stored therein. The chips corresponding to one frame of spreading codes stored in input spreading code register 71b are transferred to a spreading code register for operation 71c and stored therein.
On the other hand, a received signal formed of samples each quantized to n-bit (n is an integer satisfying n≧1) is oversampled at an oversampling rate which is M times (M is an integer satisfying M≧1) as high as the chip rate of spreading codes and supplied in time-series manner to a received signal storage register 71d. In this register, received signal samples having a code length corresponding to M times the number of chips corresponding to one frame of spreading codes (hereinafter referred to as a spreading code length) are successively stored. The example shown in FIG. 16 is applied to M=2 for the purpose of simplifying description.
There is a received signal sequence that includes samples with the number thereof two times the spreading code length and is stored in received signal storage register 71d which is a shift register. Samples held in every other stages beginning from the initial stage (odd number stages) are output at a certain timing in parallel (tap outputs) each supplied to one input of a corresponding one of multipliers constituting a multiplying unit 71e. 
The chips corresponding to one frame of spreading codes stored in operation spreading code register 71c are output in parallel (tap coefficients) each supplied to the other input of a corresponding one of multipliers constituting multiplying unit 71e. 
Respective outputs of all multipliers constituting multiplying unit 71e are summed by an adding unit 71f and the resultant value is output as a correlation value at this time.
Subsequent sample of a received signal sequence is input at the next timing in received signal storage register 71d, and the samples held in respective stages are each shifted to the next stage. At this timing, those samples (tap outputs) held in the odd number stages of shift register 71d are multiplied in multiplying unit 71e by the chips (tap coefficients) corresponding to one frame of spreading codes that are fixed in shift register 71c, and the sum of resultant values is calculated by adding unit 71f to be output as a correlation value.
In this digital matched filter 71 shown in FIG. 16, received signal samples are input to received signal storage register 71d at the sampling rate two times the chip rate of spreading codes, and samples in every other stages are used as tap outputs for calculating the correlation value. Every time subsequent sample is input and the sample in each stage is shifted, the correlation value calculation is performed. Therefore, all samples of input and received signals that are oversampled are used for the correlation value calculation.
It is noted that the number of chips of spreading codes stored in operation spreading code register 71c may not the spreading code length corresponding to one frame. In other words, even if spreading codes forming one frame are partially used, received signal samples corresponding to that number of chips may be used for calculating the correlation value. Then, the peak indicates the synchronism position so that acquisition of the synchronism position is possible by product-sum operation of partial codes.
In this case, correlation value calculation can be continued by fixing part of the spreading codes of one frame in operation spreading code register 71c while remaining spreading codes of that one frame are stored in input spreading code register 71b so as to replace the spreading codes in register 71c with those in register 71b as required.
In the conventional digital matched filter shown in FIG. 16, every time each sample of a received signal sequence is input to received signal storage register 71d at the oversampling rate, in other words, for all received signal samples temporarily stored in register 71d, multiplying unit 71e and adding unit 71f perform the product-sum operation for received signals and spreading codes. A problem here is thus a remarkable increase in power consumption by the entire digital matched filter since many logic circuits operate each time the product-sum operation is performed.
Further, in the conventional digital matched filter in FIG. 16, received signal storage register 71d holds a received signal with the number of samples M times the spreading code length, and the register is accordingly constituted of a shift register having a numerical number of stages, resulting in increase in power consumption due to successive shifting operation for data samples.
A digital matched filter proposed accordingly is disclosed for example in Japanese Patent Laying-Open No. 10-285079. The proposed digital matched filter includes a received signal storage register constituted of a plurality of registers provided in parallel with respect to an input and received signal instead of the shift register, and samples of a received signal sequence supplied in time-series manner are cyclically written at a predetermined timing into the registers.
However, in the digital matched filter having the structure as described above, the received signal samples that are input are supplied commonly to the registers provided in parallel with respect to the input received signal. As a result, sample data is input to a register not at a correct write timing. Even if a register is not at the write timing and not activated, that register consumes power if it receives any signal. Therefore, even if such a digital matched filter does not employ the shift register, the consumption power as a whole increases.
A further problem is that circuits 71e and 71f for performing the product-sum operation for received signals input at the oversampling rate and spreading codes operate at a remarkably high operating frequency and consequently these circuits consume increased power resulting in increase in the consumption power of the entire digital matched filter.